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    • 专利摘要:
    Memory device, comprising an input / output interface (INT), a bus of the SPI (BUS) type coupled to the input / output interface, and a plurality of non-volatile elementary memory devices connected to the bus of the SPI type , the chip selection inputs (S-) of each elementary memory device (DSEi) being all connected to one and the same chip selection wire (FL1) of the SPI bus, the elementary memory devices (DSEi) being in further configured and controllable to behave, as viewed from the input / output interface, as a single non-volatile memory device (DSU) whose total memory space has a total memory capacity equal to the sum of the memory capacities elementary devices.
    公开号:FR3041806A1
    申请号:FR1559042
    申请日:2015-09-25
    公开日:2017-03-31
    发明作者:Francois Tailliet；Marc Battista
    申请人:STMicroelectronics Rousset SAS；
    IPC主号:
    专利说明:

    Nonvolatile memory device, for example of the EEPROM type, having a large memory capacity, for example 16Mbits
    Embodiments and embodiments of the invention relate to non-volatile memories, for example electrically programmable and erasable dead memories known as EEPROM memories or FLASH memories, in particular those intended to be connected on a serial bus, for example of the type SPI (Serial Peripheral Interface).
    At present, the aim is to produce EEPROM memories with increasingly higher densities, that is to say, ever larger memory capacities, for example several megabits.
    However, for too large memory capacity, it is not possible to realize the memory within a single chip. In this case, the total memory capacity is distributed among several memory chips. However, the control of these different memory chips can be complex and require in any case a large number of input-output resources as well as dedicated commands.
    According to one embodiment, it is proposed to simply produce a non-volatile memory device, in particular of large memory capacity, for example of the EEPROM type, from several memory chips without requiring additional resources and without requiring commands. ("Opcode") dedicated but using conventional commands.
    According to one aspect, there is provided a memory device comprising an input-output interface, an SPI-type bus coupled to the input-output interface, and a plurality of non-volatile elementary memory devices connected to the bus-type SPI.
    The chip selection inputs commonly designated by the person skilled in the art under the name "chip select", of each elementary memory device are all connected to one and the same chip selection wire of the SPI bus, that is to say say on the "chip select" wire.
    The elementary memory devices are further configured and controllable to behave, as viewed from the input / output interface as a single nonvolatile memory device whose total memory space has a total memory capacity equal to the sum elementary memory capacities of the elementary devices.
    Thus, according to this aspect, a non-volatile memory device, in particular of large memory capacity, is formed by the combination of an SPI-type bus and several elementary memory devices. And it should be noted that one and the same SPI bus chip select wire is used for all the basic memory devices instead of using a chip select wire per chip. Furthermore, the set of elementary memory devices behave as a single memory device controllable using commands ("opcode") which are conventional commands of a memory device. There is no dedicated command.
    Moreover, the total memory space is shared between the various elementary memory devices and each elementary memory is advantageously in charge of a fixed and dedicated part of this total memory space with regard to the read and write operations.
    Thus, when a chip selection command is received, each elementary memory decodes the command and executes it conditionally on the basis of the contents of the command itself and possibly the current address segment concerned.
    In other words, according to one embodiment, each elementary memory device comprises elementary control means, each elementary control means is configured to place the corresponding elementary memory device in a selected state in the presence of a signal of the elementary memory. chip selection transmitted over the bus chip select wire by a master device, for example a microcontroller, to select said single memory device, and place the corresponding elementary memory device in an unselected state in the presence of a deselecting chip transmitted on the bus chip select wire by the master device to deselect said single memory device, and each elementary control means is configured to, in the presence of at least one access control to the space total memory of said single memory device present on the input wire of d bus serial series, to execute or not said at least one memory access command by the corresponding elementary memory device according to at least the content of said command.
    More precisely, according to one embodiment, said total memory space is subdivided into a plurality of elementary memory spaces respectively allocated to said plurality of elementary memory devices, and in the presence of said memory access command associated with an address of the total memory space, each elementary control means is configured to determine whether or not the corresponding elementary memory device is concerned by said memory access command as a function of the content of at least a part of said address. In this respect, each elementary memory device is advantageously assigned an identifier on the bus corresponding to the elementary memory space allocated to it. This identifier can be obtained wired with the aid of an external pin or programmed in a nonvolatile register of the memory.
    According to one embodiment, each elementary memory device comprises an elementary status register, configured to store an elementary status word, typically one byte. Furthermore, a status word having a structure similar to the elementary status word is associated with a virtual status register of said single memory device.
    The status register of said single memory device is said to be "virtual" in that it does not physically exist in addition to the registers of the elementary statuses of the elementary memory devices. That being so, the bus master element of the SPI type, for example a microcontroller, will be able to control the single memory device to write or to read this virtual status register as if it really existed, from a word status (usually a byte) which has a structure analogous to the elementary status words usually used in memory devices. For this purpose, we will use the set of elementary status registers and a combinatorial logic to form this virtual status register and this will be totally transparent for the microcontroller which, using the conventional commands of writing and editing. status register reading will be able to modify some bits of the virtual status register or read the entire virtual status register as if it were interrogating a single memory device physically having a status register.
    Thus, according to one embodiment, each elementary memory device comprises elementary control means or control logic, and in the presence of a write command of said virtual status register, for example designated by the acronym WRSR ("Write Status"). Register "), each elementary control means is configured to decode said command and at least according to the current values of certain bits of the status word, present in the elementary status registers, for example the values of the bits designated under the acronym -SWL ("Write Enable Latch") SRWD ("Status Register Write Disable"), and possibly depending on the logical state of a pin of each elementary memory device (known to those skilled in the art under the acronym WP ("Write Protect"), the basic control means are configured to either not perform said command or all exec er said command so as to respectively write in all the elementary status registers the same values for the concerned and respective bits.
    According to one embodiment, the status word associated with the virtual register comprises a specific bit (designated, for example, by the acronym WIP ("Write In Progress"), representative of the presence or absence of a cycle. writing to the total memory space of the single memory device This specific bit has the same function, but related to the total memory space, as the elementary specific bit WIP present in a memory register. elementary status of a non-volatile elementary memory.
    And, in the presence of a command for reading the virtual status register, for example an RDSR command ("Read Status Register"), the elementary control means of only one of the elementary memory devices, for example the one having the rank identifier 0, is configured to derive the value of said virtual status register specific bit (WIP) from the values of the peer elementary specific bits (WIP) of all the elementary status registers, and output that elaborate specific bit (WIP) ) as well as the other elementary status bits that correspond to the other bits of the status word associated with the virtual status register. In this regard, the elementary control means of the other elementary memory devices (those for example assigned identifiers of different ranks of 0) are advantageously configured to deliver sequentially the values of their specific elementary bits (WIP) on the bus at the rate of clock signal for clocking the bus, instead of unused bits of an elementary status word.
    According to one embodiment, each elementary memory device comprises a basic write authorization circuit, commonly designated by the person skilled in the art under the acronym WEL ("Write Enable Latch") having a first state. in which it stores a first logical value, for example equal to "1", corresponding to a write permission in the elementary memory space or in the elementary status register, and a second state in which it stores a second value, for example "0", corresponding to a non-write permission in the elementary memory space or in the elementary status register.
    A write authorization bit is then associated with a virtual write authorization circuit for writing said single memory device, the logical value of this bit, which may also be designated by the acronym WEL, is equal to the logic values of the corresponding elementary bits stored in the elementary latch circuits.
    Said first logical value of this WEL bit ("1" for example) thus corresponds to a write authorization in the total memory space or in the virtual status register while the second logic value of this bit ("0" per example) is a write-off in the total memory space or in the virtual status register. Here again, the "virtual" character of the write authorization lock circuit means that this virtual latch circuit does not exist physically in addition to the elementary write authorization latch circuits, but the microcontroller will be able to write in this circuit "virtual" lock as if it really existed.
    Each elementary control means is configured to position the corresponding write authorization elementary latch circuit in its first state in the presence of a first specific positioning command of said virtual write authorization circuit present on the bus, by for example a command designated by the acronym WREN ("Write Enable") and each elementary control means is configured to position the elementary write authorization lock circuit in its second state in the presence of a second specific command positioning said virtual write authorization circuit circuit present on the bus, for example a command designated by the acronym WRDI ("Write Disable"), or the execution of a write command in the virtual status register, for example a command designated by the acronym WRSR (Write Status Reg ister), or else executing a write command in a memory location of the elementary memory space of at least one of the elementary memory devices.
    If we now return to the memory access commands, when it is a write access command, a basic control means is advantageously configured to execute the write in the memory space of the memory device corresponding elementary memory device is actually affected by said write access command, if the memory location designated by said address does not belong to a write-protected memory zone and if the elementary authorization latch circuit Write (WEL) is set in its first state (WEL = 1).
    When the memory access control is a read access command, an elementary control means is advantageously configured to execute the reading in the elementary memory space of the corresponding elementary memory device if the corresponding elementary memory device is concerned. by said read access command.
    The read access control may sequentially relate to a plurality of basic memory devices. In this case, the elementary control means of the first elementary memory device concerned is configured to execute said command, then to release the bus and place the first elementary memory device in a state of rest so that the device The next elementary memory concerned may in turn take over the bus and so on until the last elementary memory device concerned executes said read access command. For example, the memory device may include two or four basic memory devices. Thus, by way of nonlimiting example, with four memory devices each having an elementary memory capacity of 4 Mbits, it is possible to form a single memory device having a memory capacity of 16 Mbits.
    The memory device may for example be encapsulated in a housing so as to form a single chip accessible by a bus of the SPI type, the elementary memory devices may for example be stacked in the housing.
    The elementary memory devices can be of the EEPROM type or of the FLASH type so as to form a single high capacity EEPROM or FLASH memory. Other advantages and characteristics of the invention will appear on examining the detailed description of non-limiting embodiments and the accompanying drawings, in which: FIGS. 1 to 24 schematically illustrate various embodiments of a memory device according to the invention.
    In FIG. 1, the reference DIS designates a single memory device, for example of the EEPROM type, connected on a bus referenced BUS of the SPI type to a master element 1, for example a microcontroller, via an interface of FIG. INT input-output.
    In the rest of the text, and for purposes of simplification, certain elements and / or signals and / or bits will be designated by references identical to Anglo-Saxon acronyms commonly known to those skilled in the art.
    The BUS bus is a four-wire SPI bus FL1, FL2, FL3, FL4.
    The first wire FL1 is a wire intended to convey a chip selection or chip deselection signal (S-signal: "Chip Select") which is in the low state for the selection and in the high state for deselection. .
    The FL2 wire is a son intended to convey serial data input (signal D: "serial data in").
    The wire FL3 is a wire intended to convey a serial clock signal (C: "serial clock") and the wire FL4 is a wire intended to convey the serial outputs (Q: "serial ouput").
    The DIS device here comprises four basic memory devices, EEPROM type, referenced DSEO, DSE1, DSE2 and DSE3.
    Each elementary memory device DSEi comprises a chip selection input S- coupled to the wire FL1 and to the corresponding input-output S- of the interface INT. Each device DSEi also has an input D connected to the wire FL2 and therefore to the input D of the interface INT, a clock input C connected to the wire FL3 and thus to the input C of the interface INT, a Q output connected to the FL4 wire, and therefore to the Q output of the INT interface.
    Each elementary memory device DSEi further comprises an identifier idi which will be discussed in more detail below on the nature and function.
    As will be seen in more detail below, the elementary memory devices DSE0-DSE3 are further configured to be controllable so as to behave, as seen from the input / output interface INT, as a single memory device DIS. whose total memory space has a total memory capacity equal to the sum of the basic memory capacities of the elementary devices.
    This is illustrated schematically in FIG. 2 in which the four elementary memory devices DSEi have been replaced by a single EEPROM memory device, referenced DSU, connected on the four wires FL1-FL4 of the bus SPI via a S-chip selection input, D and C inputs and Q output. This is seen by the master element 1 or microcontroller when it controls the memory device DIS.
    These four basic memory devices DSEi can be stacked within the same housing.
    As illustrated in FIG. 3, each elementary memory device DSEi is supplied between a supply voltage Vcc and ground and essentially comprises conventional means known per se and characteristic of an EEPROM memory.
    More precisely, the memory plane PM, of conventional structure and known per se, comprises EEPROM-type CEL memory cells.
    An XDCD column decoder and a YDCD line decoder make it possible to address the memory plane.
    These decoders are themselves addressed by an ADRG address shift register.
    There is also provided a DRG data shift register connected to the memory plane via the XDCD decoder.
    The addresses and data can be retrieved by the address registers ADRG and DRG data respectively and the data can be retrieved via the DRG data register.
    An AMPL block of sense amplifiers is also connected between the XDCD decoder and the DRG register and used for reading.
    The elementary memory device DSEi also comprises an elementary status register SRGi connected to the DRG data register.
    The memory device also comprises a basic write authorization circuit WELi which, as will be seen in more detail below, has a first state in which it stores a first logical value corresponding to a write authorization in the elementary memory space or in the elementary status register, and a second state in which it stores a second value corresponding to a write-off in the elementary memory space or in the elementary status register.
    Lastly, MGHV high voltage generation means including in particular a charge pump and its associated regulation, make it possible to generate the high voltage, typically of the order of 15 volts, to enable the operation of writing data into the memory , typically having an erase step followed by a programming step. All of these means is controlled by a control logic or elementary control means LG.
    Compared to a conventional EEPROM, some minor modifications are made in the address register ADRG which has additional stages as well as in the control logic.
    The elementary memory device DSEI further comprises conventional pins D, C, S- and Q, and a pin WP for performing a write hardware protection of the device DSEi. The logic state of the WP pin conditions the writing in the SRGi elementary status register in conjunction with a SRWDi bit ("Status Register Write Disable") which makes it possible to define whether or not the elementary status register is write-protected.
    Referring now more particularly to FIG. 4, it can be seen that the chip selection / deselection signal S-, transmitted by the microcontroller 1 on the wire FL1 of the bus, is transmitted to all the elementary memory devices DSEi.
    As a result, when the microcontroller 1 transmits on the chip select wire the signal S- in the low state to select said single memory device DSU, each elementary control means LG is configured to place the corresponding elementary memory device DSEi in a selected state.
    Similarly, when the microcontroller 1 deselects the single memory device DSU, the basic logic of the corresponding memory device DSEi places this elementary memory device in an unselected state.
    As indicated above, each elementary memory device DSEi comprises a basic write authorization circuit WELi.
    So that the microcontroller 1 can also authorize non-writing in the total memory space or in, as will be seen in more detail below, a virtual status register of said single memory device DSU, a Write Enable Latch (WEL) bit is associated with a Write Enable Latch (WEL) virtual write lock of said single DSU memory device (Figure 5). For simplification purposes, the bit associated with the virtual lock has the same WEL reference as the virtual lock itself.
    This write authorization lock circuit WEL is virtual in the sense that it does not physically exist in addition to the elementary lock circuits WELi but in fact comprises all the elementary write authorization circuits WELi.
    The logical value of the WEL bit is equal to the logical values of the WELi bits stored in the elementary latch circuits.
    Thus, the first logical value of this WEL bit, "1" for example, corresponds to a write authorization in the total memory space or in the virtual status register of the DSU memory device while the second logical value of the bit WEL, "0" for example, corresponds to a write-off in the total memory space or in the virtual status register.
    As illustrated in FIG. 6, each elementary memory device comprises an elementary status register SRGi configured to store an elementary status word, here a byte, MSTi.
    In this exemplary embodiment, characteristic of an EEPROM memory, the first bit of the status byte MSTi is the SRWDi bit ("Status Register Write Disable") which makes it possible to define whether or not the elementary status register is protected. in writing.
    Thus, if this bit is equal to 1 and the WP pin is 0, then the elementary status register is write-protected.
    If these conditions are not met, the status register can be changed to write.
    The bits b2, b3 and b4 are unused bits and are equal to 0 here.
    The bits b5 and b6, respectively referenced BPli and BPOi make it possible to define possible memory zones protected in writing.
    Thus, for example, if the two bits BPli and BPOi are equal to 0, there is no write protected memory area.
    If the bit BPI is equal to 0 and the bit BPO is equal to 1, then the memory zone of the elementary memory space protecting the write is that located in the lower quarter of the elementary memory space.
    If the BPI bit is equal to 1 and the BPO bit is equal to 0, then the write protected area of the elementary memory space is equal to the lower half of this elementary memory space.
    If the two bits BPI and BPO are equal to 1, then all of the elementary memory space is write-protected.
    Bit b7 is actually the WELi bit.
    Finally, bit b8 referenced WIPi ("Write In Progress") is a bit representative of the presence or absence of a write cycle being executed in the elementary memory space of the corresponding elementary memory device .
    More precisely, if this bit is equal to 1, then a write cycle is running in the elementary memory space and this is not the case if this bit is equal to 0.
    As illustrated in FIG. 7, an MST status word, here a byte, having a structure similar to the elementary status word MSTi is associated with a virtual status register SRGV of said single memory device DSU.
    This SRGV status register is said to be virtual in the sense that it does not exist as a physical register alone but comprises all the elementary status registers SRGi thus, as will be seen in more detail below, that a logic circuit for developing the eighth bit b8 of this MST status word, in this case the WIP bit. The MST status byte therefore comprises the SRWD bit, three bits b2-b4 equal for example to 0, the BPI and BPO bits, the WEL bit and finally the WIP bit.
    As indicated above, the SRWD bit makes it possible to define a write protection of the SRGV register and the BPI and BPO bits make it possible to define memory zones of the total memory space that are write-protected.
    The WIP bit defines the presence or absence of a running write cycle in the total memory space of the total device DSU.
    Referring now to FIGS. 8 and following to illustrate the behavior of the memory device DIS in the presence of different commands ("opcode")
    FIG. 8 illustrates the case where the microcontroller 1 sends on the FL2 wire of the bus SPI (wire D) the command WREN (Write Enable) which aims to position the circuit virtual lock write authorization WEL in its first state (equal at 1, for example).
    In this case, as illustrated in FIG. 8, each elementary control means is configured to position the corresponding write authorization elementary latch circuit WELi also in its first state (equal to 1).
    FIGS. 9 to 11 illustrate more precisely the situations in which the virtual latch circuit WEL and each elementary latch circuit WELi are positioned in their second state (equal to 0). This is the case when the microcontroller sends on the FL2 wire of the bus a specific command WRDI (Write Disable). In this case, each elementary control means unconditionally executes this command and returns the corresponding elementary latch circuit WELi to 0.
    As illustrated in FIG. 10, the virtual latch circuit WEL and each elementary latch circuit WELi can also be reset to the execution of a write status register (WRSR) write command of the virtual status register. This is also the case, as illustrated in FIG. 11, at the execution of a valid WRITE write command sent by the microcontroller 1.
    As will be seen in more detail below, even if such a WRITE command is executed by only one of the elementary memory devices DSEi, each elementary device on the bus detects the conditions of the execution of such a command Write and repositions its elementary lock circuit WLi at 0.
    In practice, this may occur, for example, during the ascent of the signal S- in the high state, which feedback initiates if necessary the non-volatile write cycles.
    Thus, at every moment, all the elementary latch circuits WELi and consequently the virtual latch circuit WEL are synchronized, that is to say that they contain the same logic value.
    Referring now more particularly to Figs. 12 to 14, to illustrate writes and reads in the total memory space of said single DSU memory device.
    It is assumed in this regard that each elementary memory device DSEI knows that the invention is implemented, that is to say that there is more than one elementary memory device on the bus.
    It is also assumed that each elementary device knows the number of elementary memory devices on the bus as well as its identifier on the bus. The indication of the implementation of the invention (more than one elementary memory device on the bus) can be obtained using an external pin or a nonvolatile configuration bit.
    The number of elementary memory devices on the bus can also be known using another nonvolatile configuration bit.
    Thus, by way of example, a zero value for this configuration bit means that there are two basic memory devices on the bus and a value 1 for this bit means, for example, that there are four basic memory devices. on the bus. Upon initialization, all the basic memory devices on the bus can write this configuration bit in parallel with the same value.
    Moreover, as indicated above, each elementary memory device DSEI is allocated the identifier idi.
    This identifier can be determined physically by an external pin.
    Thus, in the case of two basic memory devices on the bus, this external ground-welded pin gives the identifier idO to the elementary memory device DSEO while this external pin soldered to the supply voltage confers on the memory device elementary corresponding identifier idl.
    In the case of four basic memory devices on the bus, four resistors with four different values can be used. Each resistor has one terminal connected to the supply voltage and the other connected to one of the pins of a basic memory device.
    A nonvolatile register may also be used to store the value of the identifier for each elementary memory device.
    In addition, each elementary memory device is allocated a known fixed elementary memory space of the total memory space. Thus, knowing the number of elementary memory devices on the bus and its identifier, each elementary memory device can determine the address segment which it is in charge.
    Thus, for example, in the case of a total memory space having a memory capacity of 16Mbits formed by four elementary memory spaces of 4Mbits each, the total address segment varies from 00 00 00 to 1F FF FF.
    And, in this case, the elementary memory device having the identifier idO can handle the address segment varying from 000000 to 07 FF FF.
    The elementary memory device having the identifier id1 can handle the address segment ranging from 080000 to 0F FF FF.
    The basic memory device having the identifier id2 can handle the address segment ranging from 100000 to 17 FF FF.
    The elementary memory device having the identifier id3 can handle the address segment ranging from 180000 to 1F FF FF. Other situations may be possible.
    Thus, the value of the identifier can be connected to the address parity (in the case where two elementary memory devices are located on the bus) or to the congruence modulo 4 (if 4 elementary memory devices are located on the bus.
    Thus, in the latter case, an elementary memory device having an identifier equal to 0 can handle the addresses of type XX XX XX 00.
    An elementary memory device having an identifier equal to 1 can handle addresses of the type XX XX XX 01.
    An elementary memory device having an identifier equal to 2 can handle the addresses of the type XX XX XX 10 while the elementary memory device having an identifier equal to 3 can handle the addresses of the type XX XX XX 11.
    FIG. 12 illustrates the case of a WRITE memory access control associated with an address @ of the total memory space of the DSU device and to data data. In practice, the command "opcode" WRITE is sequentially followed by the address @ and data data.
    When such a command is received, all the elementary control means LG of the elementary memory devices decode it and compare, for example, the most significant bits (1 or 2) of the received address with their identifier (consisting of 1 or 2 bits).
    The elementary memory device whose value of the identifier corresponds to the (x) most significant bit (s) of the received address will execute the write command while the other elementary memory devices will remain in the a state of rest.
    Thus, at a given instant, only an elementary memory device can write data, provided of course that the write operation is authorized (WELi = 1) and that the address does not belong to a defined protected area ZP by the BPI and BPO bits.
    In practice, the elementary memory device concerned will prepare the write cycle while the signal S- is in the low state and execute it at the rising edge of this signal S-.
    FIG. 13 illustrates the case of a read command READ associated with an address @ sent by the microcontroller to the memory device DSU. On receipt of this READ command, all the elementary memory device elementary control means decode it and will compare the most significant bit (s) of the received address with their identifier. Here again, the device DSEi whose identifier corresponds to the (x) most significant bit (s) of the address will execute the read command while the other basic memory devices will remain in the state of read rest.
    As illustrated in FIG. 14, the READ read command being sequential, the data data is sequentially delivered with the address register incremented by one by each read byte.
    Thus, an elementary memory device, for example one that has the identifier idO, will continue to deliver the data data as the current address is in its address segment. As soon as the address reaches the end of its segment, the DSEO device delivers the last data, releases the bus, and returns to a state of rest.
    Each elementary memory device having its address register synchronized to the current address, the elementary memory device having the following identifier, will then take control of the bus and output the data contained in its own segment, and so on .
    This is totally transparent for the master element, namely the microcontroller 1.
    FIG. 15 illustrates the case of a Write Status Register (WRSR) write command in the virtual status register issued by the microcontroller 1 on the bus wire FL2.
    This command is used to write the non-volatile bits SRWD, BPI and BPO of the MST status word.
    This command will be decoded unconditionally by all the basic memory devices.
    That being so, according to the current values of the bits WELi, SRWDi and the logic state of the WP pin, no elementary control means LG will execute said command or all the elementary control means of the elementary memory devices will make executing said command and having the same value programmed for the SRWi, BPI, and BPO bits of all the elementary status registers.
    Figures 16 to 24 illustrate the case of an RDSR command ("Read Status Register") issued by the microcontroller 1 for the purpose of reading the virtual status register.
    In order to avoid any conflict on the FL4 (Q) wire of the SPI bus, only one elementary memory device at a time can deliver data on that wire.
    Thus, it is provided that a single elementary memory device, for example the DSEO device, outputs the SRWD, BPI, BPO, WEL and WIP bits of the virtual status register.
    In order for the memory device DSU to behave as a single memory device, the WIP bit of the virtual status register must be read at 1 if at least one of the elementary memories DSEi is performing a cycle. and 0 if none of the basic memories is executing a write cycle.
    However, each elementary memory device DSEi is not aware by default of the end or not of a write cycle performed by the other elementary memories.
    In particular, in order to deliver the WIP bit, the elementary memory device having the identifier 0 (DSEO) must know the status of the other three memory devices on the bus.
    A solution to this problem provides that the elementary memory devices DSE1-DSE3 sequentially transmit the values of their specific bit WIPi to the rhythm of the clock signal CK instead of the unused bits 000 of the elementary status registers.
    This will be explained in more detail below.
    Referring to FIG. 16, it can be seen that on the first falling edge FD1 of the clock signal CK, the elementary memory device DSEO transmits the SRWDO bit of its elementary status register, which corresponds to the SRWD bit of FIG. virtual status register.
    Then, the DSEO device releases the bus on the second falling edge FD2 of the clock signal.
    The elementary memory device DSE1 then delivers its bit WIP1 on the second falling edge FD2 of the clock signal CK instead of an unused bit, and then releases the bus on the third falling edge FD3 of the signal CK (FIG. 17). .
    The elementary memory device DSE2 then delivers its bit WIP2 on the third falling edge FD3 of the clock signal CK instead of an unused bit, and then releases the bus on the fourth falling edge FD4 (FIG. 18).
    The elementary memory device DSE3 then delivers the WIP3 bit on the fourth falling edge FD4 of the clock signal CK in place of an unused bit and then releases the bus on the fifth falling edge FD5 (FIG. 19).
    The basic memory device DSEO, which has stored the WIPO, WIP1, WIP2 and WIP3 bits in temporary registers, can then be determined by means of a logic gate PL, typically an OR logic gate, the WIP bit from these bits. four bit values (Figure 20).
    The elementary memory device DSEO then delivers the bit BPI on the falling edge FD5 of the clock signal CK (FIG. 21), then the bit BPO on the falling clock edge FD6 (FIG. 22), then the bit WEL (which is equal to the WELO bit) on the falling edge FD7 (FIG. 23) and finally the WIP bit produced on the falling edge FD8 of the clock signal CK.
    As a conventional memory device, therefore, eight downstream clock fronts were required to transmit the 8 bits of the MST status word, thus rendering this operation transparent to the microcontroller 1.
    It is also possible for the single memory device DSU to chain a write command (WRITE) with an attempt to read the memory array or an attempt to write access to the memory array or the virtual status register. that is, to chain commands WRITE and READ or WRITE and WREN + WRITE or WRITE and WREN + WRSR. In this respect two embodiments can be envisaged.
    According to a first embodiment, during writing, the microcontroller is configured to read the WIP bit of the virtual status register by making loop reads of the virtual status register, and when the WIP bit drops back to 0, the Single DSU memory device is considered to be ready to receive a next READ command or WREN + WRITE or WREN + WRSR.
    According to a second embodiment, it is used that the maximum write time (5ms for example) is generally known. In this case, the microcontroller is configured to wait for a duration equal to the maximum write time after raising the signal S-, and then, without interrogating the WIP bit, launch the next command READ or WREN + WRITE, or WREN + WRSR .
    权利要求:
    Claims (16)
    [1" id="c-fr-0001]
    A memory device, comprising an input / output interface (INT), a bus of the SPI (BUS) type coupled to the input / output interface, and a plurality of non-volatile elementary memory devices connected on the bus of the SPI type, the chip selection inputs (S-) of each elementary memory device (DSEi) being all connected to a single chip selection line (FL1) of the SPI bus, the elementary memory devices (DSEi) being further configured and controllable to behave, as viewed from the input / output interface, as a single non-volatile memory device (DSU) whose total memory space has a total memory capacity equal to the sum of the basic memory capabilities of elementary devices.
    [2" id="c-fr-0002]
    The apparatus of claim 1, wherein each elementary memory device (DSEi) comprises elementary control means (LG), each elementary control means is configured to place the corresponding elementary memory device (DSEi) in a selected state. in the presence of a chip select signal (S- = 0) transmitted over the bus chip select wire by a master device (1) to select said single memory device (DSU) and place the elementary memory device corresponding in a deselected state in the presence of a chip deselecting signal (S- = 1) transmitted on the chip selection wire of the bus by the master device to deselect said single memory device (DSU), and each means of Elementary Control (LG) is configured for, in the presence of at least one access control (WRITE, READ) to the memory space of said single memory device present e on the serial data input wire (FL2) of the bus, to execute or not said at least one memory access command by the corresponding elementary memory device according to at least the content of said command.
    [3" id="c-fr-0003]
    3. Device according to claim 2, wherein said total memory space is subdivided into a plurality of elementary memory spaces respectively allocated to said plurality of elementary memory devices, and in the presence of said memory access command and including an address (@) of the total memory space, each elementary control means is configured to determine whether the corresponding elementary memory device (DSEi) is concerned or not by said memory access command according to the content of at least a part of said address
    [4" id="c-fr-0004]
    4. Device according to claim 3, wherein each elementary memory device (DSEi) is assigned an identifier (idi) on the bus corresponding to the elementary memory space allocated to it.
    [5" id="c-fr-0005]
    5. Device according to one of claims 1 to 4, wherein each elementary memory device comprises an elementary status register (SRGi) configured to store an elementary status word (MSTI) and a status word (MST) having a Similar structure to the elementary status words is associated with a virtual status register (SRGV) of said single memory device (DSEI).
    [6" id="c-fr-0006]
    Apparatus according to claim 5, wherein each elementary memory device comprises elementary control means (LG), and in the presence of a write command (WRSR) of said virtual status register, each elementary control means is configured to decode said command and at least according to the current values of certain bits (WEL, SRWD) of said status word present in the elementary status registers, the elementary control means are configured to either not execute said command or all executing said command so as to respectively write in all the elementary status registers the same values for the respective concerned bits.
    [7" id="c-fr-0007]
    7. Device according to claim 5 or 6, wherein the status word (MST) associated with the virtual status register comprises a specific bit (WIP) representative of the presence or absence of a current write cycle. in the total memory space of said single memory device (DSU), and in the presence of a read command of the virtual status register (RDSR), the elementary control means of only one of the memory devices elementary is configured to derive the value of said specific bit (WIP) from the values of the peer specific bits (WIPi) of all the elementary status registers, and to output that elaborate specific bit (WIP) as well as the other bits of its word elementary statuses that correspond to the other bits of said status word associated with the virtual status register.
    [8" id="c-fr-0008]
    8. Device according to claim 7, wherein the elementary control means of the other memory devices are configured to sequentially output the values of their specific bit (WIP1-WIP3) on the bus at the rate of the clock signal for clocking the clock. bus instead of unused bits of elementary status words (MSTi).
    [9" id="c-fr-0009]
    9. Device according to one of claims 1 to 8, wherein each elementary memory device (DSEi) comprises a basic write authorization circuit (WELi) having a first state in which it stores a first logic value ( WELi = 1) corresponding to a write authorization in the elementary memory space or in the elementary status register, and a second state in which it stores a second value (WELi = 0) corresponding to a non-write authorization in the elementary memory space or in the elementary status register, and a write authorization bit (WEL) is associated with a write authorization virtual latch circuit of said single memory device (DSU), the logical value of this bit (WEL) being equal to the logic values of the bits (WELi) stored in the elementary latch circuits, said first logic value of this bit (WEL = 1) corresponding to a write permission in the total memory space or in the virtual status register while said second logical value of this bit (WEL = 0) corresponding to a write-off in the total memory space or in the register virtual status.
    [10" id="c-fr-0010]
    The apparatus according to claim 9, wherein each elementary memory device comprises elementary control means and each elementary control means is configured to position the corresponding elementary write-enable lock circuit (WELi) in its first state. the presence of a first specific positioning command of said write enable virtual latch circuit (WREN) present on the bus, and each elementary control means is configured to position the elementary write authorization latch circuit in its second state in the presence of a second specific command for positioning said virtual write authorization write circuit (WRDI) present on the bus or the execution of a write command (WRSR) in the virtual status register or executing a write command (WRITE) in a memory location of the space m elementary memory of any one at least of the elementary memory devices.
    [11" id="c-fr-0011]
    11. Device according to claim 3 or 4 taken in combination with one of claims 5 to 10, wherein when the memory access control is a write access control (WRITE), an elementary control means (LG ) is configured to execute the write in the elementary memory space of the corresponding elementary memory device (DSEi) if the corresponding elementary memory device (DSEi) is concerned by said write access command, if the memory location designated by said address does not belong to a write protected memory zone, and if the elementary write permission circuit (WELi) is set in its first state (WELi = 1).
    [12" id="c-fr-0012]
    The device of claim 3 or 4, taken in combination with one of claims 5 to 11, wherein when the memory access control is a read access control (READ), a basic control means is configured to execute the reading in the elementary memory space of the corresponding elementary memory device if the corresponding elementary memory device is concerned by said read access command.
    [13" id="c-fr-0013]
    The apparatus of claim 12, wherein when the read access control (READ) sequentially relates to a plurality of elementary memory devices, the elementary control means of the first elementary memory device concerned is configured to execute said command, and then releasing the bus and placing the elementary memory device in a state of rest so that the next elementary memory device concerned can in turn take hold of the bus, and so on until the last device elementary memory concerned executes said command.
    [14" id="c-fr-0014]
    14. Device according to one of the preceding claims, comprising four basic memory devices (DSE0-DSE3) each having an elementary memory capacity of 4 Mbits, the single memory device having a memory capacity of 16 Mbits.
    [15" id="c-fr-0015]
    15. Device according to one of the preceding claims, encapsulated in a housing, the elementary memory devices (DSEi) being for example stacked.
    [16" id="c-fr-0016]
    Device according to one of the preceding claims, wherein the elementary memory devices (DSEi) are of the EEPROM type.
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    同族专利:
    公开号 | 公开日
    CN205405484U|2016-07-27|
    US9753665B2|2017-09-05|
    CN106557279A|2017-04-05|
    US20170337007A1|2017-11-23|
    US20170090813A1|2017-03-30|
    US10275173B2|2019-04-30|
    FR3041806B1|2017-10-20|
    CN106557279B|2019-08-06|
    CN110265070A|2019-09-20|
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1559042A|FR3041806B1|2015-09-25|2015-09-25|NON-VOLATILE MEMORY DEVICE, FOR EXAMPLE OF THE EEPROM TYPE, HAVING IMPORTANT MEMORY CAPACITY, FOR EXAMPLE 16MBITS|FR1559042A| FR3041806B1|2015-09-25|2015-09-25|NON-VOLATILE MEMORY DEVICE, FOR EXAMPLE OF THE EEPROM TYPE, HAVING IMPORTANT MEMORY CAPACITY, FOR EXAMPLE 16MBITS|
    CN201610105456.3A| CN106557279B|2015-09-25|2016-02-25|Non-volatile memory devices with memory-size|
    US15/053,950| US9753665B2|2015-09-25|2016-02-25|Non-volatile memory device having a memory size|
    CN201910460332.0A| CN110265070A|2015-09-25|2016-02-25|Non-volatile memory devices with memory-size|
    CN201620143885.5U| CN205405484U|2015-09-25|2016-02-25|Memory device|
    US15/672,475| US10275173B2|2015-09-25|2017-08-09|Non-volatile memory device having a memory size|
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